conspiracion/rtl/if_common/if_rst_sync.sv, branch masterLinux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.rtl: fix quartus errors: parser, synthesis, fitter2024-05-24T11:58:19+00:00Alejandro Sotoalejandro@34project.org2024-05-16T07:08:04+00:00b21c321a059e11edeece1c90d97776bb0716d7a0