conspiracion/rtl/gfx/fp_add.sv, branch master Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. rtl/gfx: rename modules 2023-11-10T07:43:02+00:00 Alejandro Soto alejandro@34project.org 2023-11-03T04:19:26+00:00 d5de20fade70a0d454e3aa0087313ca715ff8759 






ip: add ip_fp_inv
2023-11-03T04:20:23+00:00

Alejandro Soto
alejandro@34project.org

2023-10-31T23:52:27+00:00

814eb9d024a928380815a8a830eee3b86d71cf75












rtl/gfx: implement fp16 on verilator
2023-10-27T11:55:35+00:00

Alejandro Soto
alejandro@34project.org

2023-10-27T11:55:35+00:00

7baed021cdf61891bc9454050edf7f2a0f75b45b












rtl/gfx: reimplement multiplier as a much smaller mat-vec pipeline
2023-10-22T06:16:50+00:00

Alejandro Soto
alejandro@34project.org

2023-10-22T06:16:40+00:00

c1c1f1e823099c82d02e94827a64d7a0b223048e












ip: downgrade to 16-bit floats
2023-10-21T21:37:45+00:00

Alejandro Soto
alejandro@34project.org

2023-10-21T21:37:45+00:00

a14fc04f3b9f5bcef941ea79c794532d7ca0e7fc












rtl/gfx: implement non-synthesizable matrix multiplier
2023-10-21T09:21:18+00:00

Alejandro Soto
alejandro@34project.org

2023-10-21T09:21:18+00:00

d84718bf7955a6bba03aa44938f0f140c1a6390d