conspiracion/rtl/core/shifter.sv, branch ce3201 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Fix shr carry bug 2022-11-16T03:37:20+00:00 Alejandro Soto alejandro@34project.org 2022-11-16T03:37:16+00:00 84e9a917a31f39eaf333d1fc69b30d13e7640c7a 






Fix zero-extended (lsr) vs sign-extended (asr) shifts
2022-10-23T21:35:32+00:00

Alejandro Soto
alejandro@34project.org

2022-10-23T21:34:57+00:00

40482e26534ac5d0deb9500d205d47ac9a99c3a5












Major shifter-ALU redesign
2022-10-02T15:49:48+00:00

Alejandro Soto
alejandro@34project.org

2022-10-02T15:49:48+00:00

e97d445908f39a3a1a215a824f52b283147e6195

The shifter unit now works in parallel with the ALU and is no longer
part of it. Instructions that use the shifter as input to the ALU will
now take an additional cycle, unless the control unit can detect a
"trivial shift" situation where the shifter's output will be the same as
its input. This change improves Fmax substantially.





The shifter unit now works in parallel with the ALU and is no longer
part of it. Instructions that use the shifter as input to the ALU will
now take an additional cycle, unless the control unit can detect a
"trivial shift" situation where the shifter's output will be the same as
its input. This change improves Fmax substantially.