conspiracion/rtl/core/regs, branch ce4302/p1

conspiracion/rtl/core/regs, branch ce4302/p1 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. rtl/core, tb: replace bus_master with a new top-level module 2023-09-26T03:33:49+00:00 Alejandro Soto alejandro@34project.org 2023-09-26T01:12:49+00:00 ed0bd705f94f6aea568ec8405534984a37770f21

Fix reset glitches 2022-11-10T16:11:33+00:00 Alejandro Soto alejandro@34project.org 2022-11-10T16:11:33+00:00 acca3eb31a051f335c51306786bb972c21634998

Implement reset 2022-11-09T15:25:48+00:00 Alejandro Soto alejandro@34project.org 2022-11-09T15:25:48+00:00 5d798386c3b1c1dc45a2fbc382c9367ccc27c524

Fix long combinational path between regs and fetch 2022-11-08T01:04:39+00:00 Alejandro Soto alejandro@34project.org 2022-11-08T01:04:39+00:00 c67a1007045a9bf0282c26da74149723c6a2941d

Rework regfile in order to remove negedge trigger 2022-11-07T23:25:11+00:00 Alejandro Soto alejandro@34project.org 2022-11-07T23:20:38+00:00 cc7ed6bd05b8143ed4250caf97798c8bbfc6b748

Use negative clock edge for register file in Verilator builds 2022-10-17T07:14:56+00:00 Alejandro Soto alejandro@34project.org 2022-10-17T07:14:56+00:00 b328dee91da704474509054043740128e5969c8b

Implement register dumps 2022-10-17T00:20:45+00:00 Alejandro Soto alejandro@34project.org 2022-10-17T00:20:45+00:00 87c73314d7ce0062b13ae14f376ec50a4653fb18

Pipeline flags writeback (breaks combinational data dependencies) 2022-10-09T20:34:48+00:00 Alejandro Soto alejandro@34project.org 2022-10-09T20:34:48+00:00 1f1f61bbab1396278a861e46fd65a50d1914585e

Fix pipeline hazards 2022-10-03T18:16:01+00:00 Alejandro Soto alejandro@34project.org 2022-10-03T18:16:01+00:00 7e7c205367558b622fa56edaaa9c76491d57a4fa

Use @(posedge clk) in register files 2022-10-02T15:53:00+00:00 Alejandro Soto alejandro@34project.org 2022-10-02T15:53:00+00:00 d7648e97a20229cdbc4c25b3d446f020e9b4a229