conspiracion/rtl/core/regs/regs.sv, branch ce3201 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Implement reset 2022-11-09T15:25:48+00:00 Alejandro Soto alejandro@34project.org 2022-11-09T15:25:48+00:00 5d798386c3b1c1dc45a2fbc382c9367ccc27c524 






Fix long combinational path between regs and fetch
2022-11-08T01:04:39+00:00

Alejandro Soto
alejandro@34project.org

2022-11-08T01:04:39+00:00

c67a1007045a9bf0282c26da74149723c6a2941d












Rework regfile in order to remove negedge trigger
2022-11-07T23:25:11+00:00

Alejandro Soto
alejandro@34project.org

2022-11-07T23:20:38+00:00

cc7ed6bd05b8143ed4250caf97798c8bbfc6b748












Pipeline flags writeback (breaks combinational data dependencies)
2022-10-09T20:34:48+00:00

Alejandro Soto
alejandro@34project.org

2022-10-09T20:34:48+00:00

1f1f61bbab1396278a861e46fd65a50d1914585e












Fix pipeline hazards
2022-10-03T18:16:01+00:00

Alejandro Soto
alejandro@34project.org

2022-10-03T18:16:01+00:00

7e7c205367558b622fa56edaaa9c76491d57a4fa












Fix branching bugs
2022-09-27T21:16:07+00:00

Alejandro Soto
alejandro@34project.org

2022-09-27T21:16:07+00:00

ec7649eef16c7f9c3ca4b74a1cea95eb2f524b29












Refactor CPSR and uarch.sv
2022-09-26T01:55:29+00:00

Alejandro Soto
alejandro@34project.org

2022-09-26T01:55:29+00:00

fa370016708149976c748c14eadad1f89cf5a8ea












Implement register file
2022-09-25T21:00:25+00:00

Alejandro Soto
alejandro@34project.org

2022-09-25T21:00:25+00:00

5dc62fde35731279e5ef4c7b334cb97d4f24f656