conspiracion/rtl/core/regs/file.sv, branch ce4302/p2

conspiracion/rtl/core/regs/file.sv, branch ce4302/p2 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Fix reset glitches 2022-11-10T16:11:33+00:00 Alejandro Soto alejandro@34project.org 2022-11-10T16:11:33+00:00 acca3eb31a051f335c51306786bb972c21634998

Implement reset 2022-11-09T15:25:48+00:00 Alejandro Soto alejandro@34project.org 2022-11-09T15:25:48+00:00 5d798386c3b1c1dc45a2fbc382c9367ccc27c524

Rework regfile in order to remove negedge trigger 2022-11-07T23:25:11+00:00 Alejandro Soto alejandro@34project.org 2022-11-07T23:20:38+00:00 cc7ed6bd05b8143ed4250caf97798c8bbfc6b748

Use negative clock edge for register file in Verilator builds 2022-10-17T07:14:56+00:00 Alejandro Soto alejandro@34project.org 2022-10-17T07:14:56+00:00 b328dee91da704474509054043740128e5969c8b

Implement register dumps 2022-10-17T00:20:45+00:00 Alejandro Soto alejandro@34project.org 2022-10-17T00:20:45+00:00 87c73314d7ce0062b13ae14f376ec50a4653fb18

Use @(posedge clk) in register files 2022-10-02T15:53:00+00:00 Alejandro Soto alejandro@34project.org 2022-10-02T15:53:00+00:00 d7648e97a20229cdbc4c25b3d446f020e9b4a229

Switch from operand forwarding to next insn stalls (improves Fmax) 2022-09-28T01:52:26+00:00 Alejandro Soto alejandro@34project.org 2022-09-28T01:52:26+00:00 5e2f6be247018699d71d32887010830ba45b8349

Fix branching bugs 2022-09-27T21:16:07+00:00 Alejandro Soto alejandro@34project.org 2022-09-27T21:16:07+00:00 ec7649eef16c7f9c3ca4b74a1cea95eb2f524b29

Fix Quartus issues 2022-09-26T01:22:43+00:00 Alejandro Soto alejandro@34project.org 2022-09-26T01:22:43+00:00 3aa075cf009d9aa8c602389853cc3ea78cda8701

Implement register file 2022-09-25T21:00:25+00:00 Alejandro Soto alejandro@34project.org 2022-09-25T21:00:25+00:00 5dc62fde35731279e5ef4c7b334cb97d4f24f656