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<title>conspiracion/rtl/core/mmu, branch ce3201</title>
<subtitle>Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.</subtitle>
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<entry>
<title>Fix spurious high bus_write in page walker</title>
<updated>2022-12-20T04:36:03+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2022-12-20T04:35:54+00:00</published>
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</entry>
<entry>
<title>Implement mode-translated memory accesses</title>
<updated>2022-12-18T19:19:55+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2022-12-18T19:19:55+00:00</published>
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<entry>
<title>Implement mode privilege checks in MMU</title>
<updated>2022-12-17T04:20:26+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2022-12-17T04:20:01+00:00</published>
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</entry>
<entry>
<title>Fix implementation of MMU access faults</title>
<updated>2022-12-16T22:29:10+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2022-12-15T01:16:54+00:00</published>
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</content>
</entry>
<entry>
<title>Implement prefetch aborts</title>
<updated>2022-12-16T22:29:10+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2022-12-12T05:54:38+00:00</published>
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</content>
</entry>
<entry>
<title>Implement MMU access checks</title>
<updated>2022-12-16T22:29:09+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2022-12-11T23:28:03+00:00</published>
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</entry>
<entry>
<title>Implement data aborts</title>
<updated>2022-12-16T22:27:20+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2022-12-11T20:48:08+00:00</published>
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</pre>
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</content>
</entry>
<entry>
<title>Implement hardware virtual memory</title>
<updated>2022-12-16T22:27:19+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2022-12-11T01:18:21+00:00</published>
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<entry>
<title>Implement rest of cp15 registers</title>
<updated>2022-12-11T01:36:38+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2022-12-11T01:36:38+00:00</published>
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</entry>
<entry>
<title>Implemente byte-enable signal in stores</title>
<updated>2022-11-16T05:31:30+00:00</updated>
<author>
<name>Alejandro Soto</name>
<email>alejandro@34project.org</email>
</author>
<published>2022-11-16T05:18:09+00:00</published>
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