conspiracion/rtl/core/isa.sv, branch ce3201

conspiracion/rtl/core/isa.sv, branch ce3201 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Move isa.sv to core/decode 2022-10-16T07:33:43+00:00 Alejandro Soto alejandro@34project.org 2022-10-16T07:33:43+00:00 f0b38daac3a2f987deb79fcca763f3b84b0f2b73

Implement most memory transactions 2022-10-10T01:25:27+00:00 Alejandro Soto alejandro@34project.org 2022-10-10T01:25:27+00:00 7d95ff01bcd8c42efe118fd1bddaabfca0e937eb

Implement LDR/STR decode 2022-10-08T21:34:46+00:00 Alejandro Soto alejandro@34project.org 2022-10-08T21:34:46+00:00 dab6e68a8396475af5acbf53397f93c6b52e2e71

Split decoding of flexible second operand out of data instructions 2022-10-02T19:23:22+00:00 Alejandro Soto alejandro@34project.org 2022-10-02T19:23:22+00:00 63ec42cc245b2da9ab97cc4eef6bbd21e08cde07

Implement shifter decoding 2022-09-26T05:21:32+00:00 Alejandro Soto alejandro@34project.org 2022-09-26T05:21:32+00:00 43829e0400f0a7aaccbb1ebefb44a38c41749e77

Refactor CPSR and uarch.sv 2022-09-26T01:55:29+00:00 Alejandro Soto alejandro@34project.org 2022-09-26T01:55:29+00:00 fa370016708149976c748c14eadad1f89cf5a8ea

Implement ALU 2022-09-25T23:46:38+00:00 Alejandro Soto alejandro@34project.org 2022-09-25T23:46:38+00:00 b5f43ef8431532b1e0b498a88072fdfd2cf81ac9

Implement register file 2022-09-25T21:00:25+00:00 Alejandro Soto alejandro@34project.org 2022-09-25T21:00:25+00:00 5dc62fde35731279e5ef4c7b334cb97d4f24f656

Implement decode of ALU instructions 2022-09-25T03:40:27+00:00 Alejandro Soto alejandro@34project.org 2022-09-25T03:40:27+00:00 5f55ae1551760b7975ae005e01e4b3c63de49a64

Add instruction encodings 2022-09-25T01:24:02+00:00 Alejandro Soto alejandro@34project.org 2022-09-25T01:24:02+00:00 cafa82ab147544e80aeec08069b35f16541e27f2