conspiracion/rtl/core/fetch/prefetch.sv, branch ce3201

conspiracion/rtl/core/fetch/prefetch.sv, branch ce3201 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Implement prefetch aborts 2022-12-16T22:29:10+00:00 Alejandro Soto alejandro@34project.org 2022-12-12T05:54:38+00:00 79e05aa7f0ccce6eb26248ddef3e928727857a9c

Implement single-stepping 2022-12-08T01:51:41+00:00 Alejandro Soto alejandro@34project.org 2022-12-08T01:18:04+00:00 c39552375661e495b344e8386649ade92a4d45b2

Implement reset 2022-11-09T15:25:48+00:00 Alejandro Soto alejandro@34project.org 2022-11-09T15:25:48+00:00 5d798386c3b1c1dc45a2fbc382c9367ccc27c524

Rework bus architecture 2022-10-16T01:31:55+00:00 Alejandro Soto alejandro@34project.org 2022-10-16T01:31:55+00:00 ec152d814af82524cf68df95d7f06b9b70c0d0d0

Implement branching in fetch stage 2022-09-27T21:12:02+00:00 Alejandro Soto alejandro@34project.org 2022-09-27T21:12:02+00:00 7fe23c697af81c08b69c0b30f1db48ed16493662

Fix prefetch PC not advancing when buffer is empty 2022-09-26T16:29:41+00:00 Alejandro Soto alejandro@34project.org 2022-09-26T16:29:41+00:00 6270090795a2897517dd435afcaa9eec9f74e027

Fetch NOP on prefetch flush 2022-09-25T21:04:41+00:00 Alejandro Soto alejandro@34project.org 2022-09-25T21:04:41+00:00 4fe334c57ea5549bbbfa1b82142ba97012e304f5

Add toplevel module for core tests 2022-09-24T05:42:05+00:00 Alejandro Soto alejandro@34project.org 2022-09-24T05:42:05+00:00 83be8cb319efc245c17512c86c494ace2ad022ff

Implement initial fetch stage 2022-09-24T05:40:09+00:00 Alejandro Soto alejandro@34project.org 2022-09-24T05:40:09+00:00 33e4434a0cb4ad7f15178a013296fb2fa740112e