conspiracion/rtl/core/decode/snd.sv, branch ce4302/p1

conspiracion/rtl/core/decode/snd.sv, branch ce4302/p1 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Fix zero-extended (lsr) vs sign-extended (asr) shifts 2022-10-23T21:35:32+00:00 Alejandro Soto alejandro@34project.org 2022-10-23T21:34:57+00:00 40482e26534ac5d0deb9500d205d47ac9a99c3a5

Fix bad decoding of second-operand immediates 2022-10-23T16:52:18+00:00 Alejandro Soto alejandro@34project.org 2022-10-23T16:52:18+00:00 de5debd2c30e9aad633b93c5bfec0780298a61d6

Fix unsafe decode signals 2022-10-17T07:14:14+00:00 Alejandro Soto alejandro@34project.org 2022-10-17T07:14:14+00:00 cf3fa9d250dcbc3d0aa0c688a62902f96e195053

Move isa.sv to core/decode 2022-10-16T07:33:43+00:00 Alejandro Soto alejandro@34project.org 2022-10-16T07:33:43+00:00 f0b38daac3a2f987deb79fcca763f3b84b0f2b73

Implement LDR/STR decode 2022-10-08T21:34:46+00:00 Alejandro Soto alejandro@34project.org 2022-10-08T21:34:46+00:00 dab6e68a8396475af5acbf53397f93c6b52e2e71

Split decoding of flexible second operand out of data instructions 2022-10-02T19:23:22+00:00 Alejandro Soto alejandro@34project.org 2022-10-02T19:23:22+00:00 63ec42cc245b2da9ab97cc4eef6bbd21e08cde07