conspiracion/rtl/core/decode/isa.sv, branch master

conspiracion/rtl/core/decode/isa.sv, branch master Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. rtl: refactor filenames and directory hierarchy 2024-02-20T17:11:17+00:00 Alejandro Soto alejandro@34project.org 2024-01-21T12:23:46+00:00 f3b18ead59ae02f95dabbf0a1dea40873a816975

rtl/core: implement ldrex/strex decode 2023-10-03T05:29:46+00:00 Alejandro Soto alejandro@34project.org 2023-10-02T17:15:34+00:00 fbe3ab39675d338eb6d5388b7deacf98a3a8ae2d

Fix decoding of msr with immediate operand 2022-12-09T01:30:32+00:00 Alejandro Soto alejandro@34project.org 2022-12-09T01:30:32+00:00 2cbccf921bf84665c55cea67b81f31c66dde4249

Implement breakpoints 2022-12-06T21:27:42+00:00 Alejandro Soto alejandro@34project.org 2022-12-06T21:27:42+00:00 b1761b8eac5777c09723bbc8cd31cc05d8ec35ae

Implement bx lr 2022-11-17T05:32:25+00:00 Alejandro Soto alejandro@34project.org 2022-11-17T01:12:28+00:00 e33c30734b475879318b4f5c178a2f3bf2090bbb

Implement psr read/write logic 2022-11-16T23:55:27+00:00 Alejandro Soto alejandro@34project.org 2022-11-16T22:46:52+00:00 683352ce030923bdef3cf4fe90d6cb73f4f74529

Fix decoding of LDST_MISC group 2022-11-16T06:03:11+00:00 Alejandro Soto alejandro@34project.org 2022-11-16T06:03:11+00:00 86903ec40acd3014861d856660a27f6a131d8ca3

Improve ALU performance 2022-11-08T21:59:12+00:00 Alejandro Soto alejandro@34project.org 2022-11-08T21:59:12+00:00 13b112dcb8f67778c6a140cb5ce8f1ab21aa6fb9

Implement decode for mrs, msr 2022-11-07T01:43:56+00:00 Alejandro Soto alejandro@34project.org 2022-11-07T01:43:51+00:00 3576202083fb46fb755ceaefb5efe228afa9e2de

Implement coprocessor instruction decode 2022-11-02T05:04:24+00:00 Alejandro Soto alejandro@34project.org 2022-11-02T03:00:50+00:00 735c804c8e8e4bdcbe27c2e8ff74d609d7f45846