conspiracion/rtl/core/decode/conds.sv, branch ce4302/p2

conspiracion/rtl/core/decode/conds.sv, branch ce4302/p2 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Register decode output in a new porch stage 2022-11-08T19:29:23+00:00 Alejandro Soto alejandro@34project.org 2022-11-08T19:00:40+00:00 f6929f9a4703e3eee9d7bd9752de055729cdd498

Move isa.sv to core/decode 2022-10-16T07:33:43+00:00 Alejandro Soto alejandro@34project.org 2022-10-16T07:33:43+00:00 f0b38daac3a2f987deb79fcca763f3b84b0f2b73

Fix flags and writeback hazards 2022-10-16T05:33:34+00:00 Alejandro Soto alejandro@34project.org 2022-10-16T05:33:34+00:00 d7747d9e030f965bd358bca5badb849f656147a8

Refactor CPSR and uarch.sv 2022-09-26T01:55:29+00:00 Alejandro Soto alejandro@34project.org 2022-09-26T01:55:29+00:00 fa370016708149976c748c14eadad1f89cf5a8ea

Implement initial decoder 2022-09-25T03:41:46+00:00 Alejandro Soto alejandro@34project.org 2022-09-25T03:41:46+00:00 601835e33298015cf49f0ab33a7ef3d61b003ad9