conspiracion/rtl/core/cp15, branch ce3201

conspiracion/rtl/core/cp15, branch ce3201 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Fix implementation of MMU access faults 2022-12-16T22:29:10+00:00 Alejandro Soto alejandro@34project.org 2022-12-15T01:16:54+00:00 d2be560fa668cefcc5eff6b88180f12fec0c326e

Add cp15 cyclecnt clock source 2022-12-16T22:29:10+00:00 Alejandro Soto alejandro@34project.org 2022-12-13T20:59:33+00:00 1f94f0eb7e214bff29468bf9c39cb99520e290f2

Fix sysctrl register dump 2022-12-16T22:29:10+00:00 Alejandro Soto alejandro@34project.org 2022-12-12T19:19:18+00:00 397245139af754af07e61a10a91fdc9b9e72153f

Show main cp15 registers in register dumps 2022-12-16T22:29:10+00:00 Alejandro Soto alejandro@34project.org 2022-12-12T17:47:02+00:00 c67d424c6d130f810c251576fd55389d1385edb5

Implement MMU access checks 2022-12-16T22:29:09+00:00 Alejandro Soto alejandro@34project.org 2022-12-11T23:28:03+00:00 d006be2e89aa493237f212811ee880ed8b54241b

Implement data aborts 2022-12-16T22:27:20+00:00 Alejandro Soto alejandro@34project.org 2022-12-11T20:48:08+00:00 ff71bcd0c5425c168f111b8f4a92d0a90a6c9c31

Expose cp15 signals to core toplevel 2022-12-11T01:56:19+00:00 Alejandro Soto alejandro@34project.org 2022-12-11T01:56:19+00:00 6b163a88179ac3073d22622be4991f332529c8bd

Implement rest of cp15 registers 2022-12-11T01:36:38+00:00 Alejandro Soto alejandro@34project.org 2022-12-11T01:36:38+00:00 8026947ecdf9b023c3720b26bf257bf46f7a2805

Implement CP15 ID register 2022-12-09T07:43:23+00:00 Alejandro Soto alejandro@34project.org 2022-12-09T07:43:23+00:00 02f76bae32e295bf1da04e38dfa12dfbc5832aec

Implement reset 2022-11-09T15:25:48+00:00 Alejandro Soto alejandro@34project.org 2022-11-09T15:25:48+00:00 5d798386c3b1c1dc45a2fbc382c9367ccc27c524