conspiracion/rtl/core/cp15/syscfg.sv, branch master Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. rtl: refactor filenames and directory hierarchy 2024-02-20T17:11:17+00:00 Alejandro Soto alejandro@34project.org 2024-01-21T12:23:46+00:00 f3b18ead59ae02f95dabbf0a1dea40873a816975 






Fix sysctrl register dump
2022-12-16T22:29:10+00:00

Alejandro Soto
alejandro@34project.org

2022-12-12T19:19:18+00:00

397245139af754af07e61a10a91fdc9b9e72153f












Show main cp15 registers in register dumps
2022-12-16T22:29:10+00:00

Alejandro Soto
alejandro@34project.org

2022-12-12T17:47:02+00:00

c67d424c6d130f810c251576fd55389d1385edb5












Expose cp15 signals to core toplevel
2022-12-11T01:56:19+00:00

Alejandro Soto
alejandro@34project.org

2022-12-11T01:56:19+00:00

6b163a88179ac3073d22622be4991f332529c8bd












Implement rest of cp15 registers
2022-12-11T01:36:38+00:00

Alejandro Soto
alejandro@34project.org

2022-12-11T01:36:38+00:00

8026947ecdf9b023c3720b26bf257bf46f7a2805