conspiracion/rtl/core/cp15/map.sv, branch master Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. rtl: refactor filenames and directory hierarchy 2024-02-20T17:11:17+00:00 Alejandro Soto alejandro@34project.org 2024-01-21T12:23:46+00:00 f3b18ead59ae02f95dabbf0a1dea40873a816975 






Add cp15 cyclecnt clock source
2022-12-16T22:29:10+00:00

Alejandro Soto
alejandro@34project.org

2022-12-13T20:59:33+00:00

1f94f0eb7e214bff29468bf9c39cb99520e290f2












Implement rest of cp15 registers
2022-12-11T01:36:38+00:00

Alejandro Soto
alejandro@34project.org

2022-12-11T01:36:38+00:00

8026947ecdf9b023c3720b26bf257bf46f7a2805












Implement CP15 ID register
2022-12-09T07:43:23+00:00

Alejandro Soto
alejandro@34project.org

2022-12-09T07:43:23+00:00

02f76bae32e295bf1da04e38dfa12dfbc5832aec












Add cp15 primary register map
2022-11-02T05:04:24+00:00

Alejandro Soto
alejandro@34project.org

2022-11-02T04:28:17+00:00

45efe8bf6148d9d1cd7127a5d245d5e3cd6b4647