conspiracion/rtl/core/cp15/cp15.sv, branch master

conspiracion/rtl/core/cp15/cp15.sv, branch master Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. rtl: refactor filenames and directory hierarchy 2024-02-20T17:11:17+00:00 Alejandro Soto alejandro@34project.org 2024-01-21T12:23:46+00:00 f3b18ead59ae02f95dabbf0a1dea40873a816975

Add cp15 cyclecnt clock source 2022-12-16T22:29:10+00:00 Alejandro Soto alejandro@34project.org 2022-12-13T20:59:33+00:00 1f94f0eb7e214bff29468bf9c39cb99520e290f2

Show main cp15 registers in register dumps 2022-12-16T22:29:10+00:00 Alejandro Soto alejandro@34project.org 2022-12-12T17:47:02+00:00 c67d424c6d130f810c251576fd55389d1385edb5

Implement MMU access checks 2022-12-16T22:29:09+00:00 Alejandro Soto alejandro@34project.org 2022-12-11T23:28:03+00:00 d006be2e89aa493237f212811ee880ed8b54241b

Implement data aborts 2022-12-16T22:27:20+00:00 Alejandro Soto alejandro@34project.org 2022-12-11T20:48:08+00:00 ff71bcd0c5425c168f111b8f4a92d0a90a6c9c31

Expose cp15 signals to core toplevel 2022-12-11T01:56:19+00:00 Alejandro Soto alejandro@34project.org 2022-12-11T01:56:19+00:00 6b163a88179ac3073d22622be4991f332529c8bd

Implement rest of cp15 registers 2022-12-11T01:36:38+00:00 Alejandro Soto alejandro@34project.org 2022-12-11T01:36:38+00:00 8026947ecdf9b023c3720b26bf257bf46f7a2805

Implement reset 2022-11-09T15:25:48+00:00 Alejandro Soto alejandro@34project.org 2022-11-09T15:25:48+00:00 5d798386c3b1c1dc45a2fbc382c9367ccc27c524

Add CPUID register 2022-11-02T05:04:24+00:00 Alejandro Soto alejandro@34project.org 2022-11-02T05:00:52+00:00 ed42ddad4a09ef6919ac3c1ee54ad17f4e8b13bc

Add the cp15 subsystem 2022-11-02T05:04:24+00:00 Alejandro Soto alejandro@34project.org 2022-11-02T03:50:18+00:00 c14209fa2a72d62e06a5480b3652fe4680978349