conspiracion/rtl/core/control/stall.sv, branch ce4302/p2 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Implement privileged ldm/stm of user registers 2022-12-19T00:31:03+00:00 Alejandro Soto alejandro@34project.org 2022-12-19T00:31:03+00:00 e290956adf94dade4c9c4cd057cca08af1c61aeb 






Implement breakpoints
2022-12-06T21:27:42+00:00

Alejandro Soto
alejandro@34project.org

2022-12-06T21:27:42+00:00

b1761b8eac5777c09723bbc8cd31cc05d8ec35ae












Implement psr read/write logic
2022-11-16T23:55:27+00:00

Alejandro Soto
alejandro@34project.org

2022-11-16T22:46:52+00:00

683352ce030923bdef3cf4fe90d6cb73f4f74529












Simplify flags datapath
2022-11-16T20:08:16+00:00

Alejandro Soto
alejandro@34project.org

2022-11-16T20:08:16+00:00

8c410eab0ea97b737ecd59cd4a1f7582f8c045cf












Convert core state machines to Quartus-inferring RTL
2022-11-13T11:54:44+00:00

Alejandro Soto
alejandro@34project.org

2022-11-13T11:22:23+00:00

d463acba5f9589085afb3dcc4058d82908ff90f2












Implement CPU halt
2022-11-13T11:54:44+00:00

Alejandro Soto
alejandro@34project.org

2022-11-13T03:47:54+00:00

6cb000adf57d7af2ec4aac8fd93d12f09cc63556












Simplify stall conditions to reflect uarch changes
2022-11-13T11:54:44+00:00

Alejandro Soto
alejandro@34project.org

2022-11-11T00:21:53+00:00

07d9046a69600bee983c464ea8ee16fe2d959729












Implement reset
2022-11-09T15:25:48+00:00

Alejandro Soto
alejandro@34project.org

2022-11-09T15:25:48+00:00

5d798386c3b1c1dc45a2fbc382c9367ccc27c524












Refactor decode signals into unified insn_decode struct
2022-11-08T06:19:49+00:00

Alejandro Soto
alejandro@34project.org

2022-11-08T06:19:49+00:00

ac0d6f4e068ff0ff08f05e04053ebd53ba20bcb8












Add PSR control signal set
2022-11-07T01:55:54+00:00

Alejandro Soto
alejandro@34project.org

2022-11-07T01:55:54+00:00

8315f5f3ea43150d250aa16575ab274913f93d2a