conspiracion/rtl/core/control/select.sv, branch ce4302/p1Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.Implement privileged ldm/stm of user registers2022-12-19T00:31:03+00:00Alejandro Sotoalejandro@34project.org2022-12-19T00:31:03+00:00e290956adf94dade4c9c4cd057cca08af1c61aeb
Implement psr read/write logic2022-11-16T23:55:27+00:00Alejandro Sotoalejandro@34project.org2022-11-16T22:46:52+00:00683352ce030923bdef3cf4fe90d6cb73f4f74529
Rewrite duplicate ldst logic as signal ldst_next2022-11-16T00:32:55+00:00Alejandro Sotoalejandro@34project.org2022-11-16T00:32:55+00:00a055bc85bc50897644e7ed62699abff46d818d5f
Convert core state machines to Quartus-inferring RTL2022-11-13T11:54:44+00:00Alejandro Sotoalejandro@34project.org2022-11-13T11:22:23+00:00d463acba5f9589085afb3dcc4058d82908ff90f2
Refactor decode signals into unified insn_decode struct2022-11-08T06:19:49+00:00Alejandro Sotoalejandro@34project.org2022-11-08T06:19:49+00:00ac0d6f4e068ff0ff08f05e04053ebd53ba20bcb8
Remove false dependencies on control.issue (long combinational)2022-11-08T01:07:55+00:00Alejandro Sotoalejandro@34project.org2022-11-08T01:07:55+00:004ccb96c1aaf348f677954171751b58ad8f4dccf1
Rework regfile in order to remove negedge trigger2022-11-07T23:25:11+00:00Alejandro Sotoalejandro@34project.org2022-11-07T23:20:38+00:00cc7ed6bd05b8143ed4250caf97798c8bbfc6b748
Quartus has not support for unique02022-11-07T20:28:50+00:00Alejandro Sotoalejandro@34project.org2022-11-07T19:52:12+00:00280cb5bb42f56d13ae2043b955a7bf286022b0b7