conspiracion/rtl/core/control/issue.sv, branch ce4302/p2 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Implement branch history (simulation only) 2022-12-16T22:29:10+00:00 Alejandro Soto alejandro@34project.org 2022-12-15T04:26:37+00:00 ae7fd6a060c9bb1ce9db83f8eb23fa19e8fa0e7a 






Implement prefetch aborts
2022-12-16T22:29:10+00:00

Alejandro Soto
alejandro@34project.org

2022-12-12T05:54:38+00:00

79e05aa7f0ccce6eb26248ddef3e928727857a9c












Implement single-stepping
2022-12-08T01:51:41+00:00

Alejandro Soto
alejandro@34project.org

2022-12-08T01:18:04+00:00

c39552375661e495b344e8386649ade92a4d45b2












Implement breakpoints
2022-12-06T21:27:42+00:00

Alejandro Soto
alejandro@34project.org

2022-12-06T21:27:42+00:00

b1761b8eac5777c09723bbc8cd31cc05d8ec35ae












Implement psr read/write logic
2022-11-16T23:55:27+00:00

Alejandro Soto
alejandro@34project.org

2022-11-16T22:46:52+00:00

683352ce030923bdef3cf4fe90d6cb73f4f74529












Fix false undefined exception
2022-11-16T03:48:08+00:00

Alejandro Soto
alejandro@34project.org

2022-11-16T03:48:08+00:00

8ab171864291c74d0a22cac911bc8a8aee8a7d5b












Convert core state machines to Quartus-inferring RTL
2022-11-13T11:54:44+00:00

Alejandro Soto
alejandro@34project.org

2022-11-13T11:22:23+00:00

d463acba5f9589085afb3dcc4058d82908ff90f2












Implement CPU halt
2022-11-13T11:54:44+00:00

Alejandro Soto
alejandro@34project.org

2022-11-13T03:47:54+00:00

6cb000adf57d7af2ec4aac8fd93d12f09cc63556












Implement reset
2022-11-09T15:25:48+00:00

Alejandro Soto
alejandro@34project.org

2022-11-09T15:25:48+00:00

5d798386c3b1c1dc45a2fbc382c9367ccc27c524












Register decode output in a new porch stage
2022-11-08T19:29:23+00:00

Alejandro Soto
alejandro@34project.org

2022-11-08T19:00:40+00:00

f6929f9a4703e3eee9d7bd9752de055729cdd498