conspiracion/rtl/core/control/branch.sv, branch master Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. rtl: refactor filenames and directory hierarchy 2024-02-20T17:11:17+00:00 Alejandro Soto alejandro@34project.org 2024-01-21T12:23:46+00:00 f3b18ead59ae02f95dabbf0a1dea40873a816975 






Convert core state machines to Quartus-inferring RTL
2022-11-13T11:54:44+00:00

Alejandro Soto
alejandro@34project.org

2022-11-13T11:22:23+00:00

d463acba5f9589085afb3dcc4058d82908ff90f2












Implement reset
2022-11-09T15:25:48+00:00

Alejandro Soto
alejandro@34project.org

2022-11-09T15:25:48+00:00

5d798386c3b1c1dc45a2fbc382c9367ccc27c524












Refactor decode signals into unified insn_decode struct
2022-11-08T06:19:49+00:00

Alejandro Soto
alejandro@34project.org

2022-11-08T06:19:49+00:00

ac0d6f4e068ff0ff08f05e04053ebd53ba20bcb8












Split branch logic out of control.sv
2022-11-06T20:19:48+00:00

Alejandro Soto
alejandro@34project.org

2022-11-06T20:19:48+00:00

76e734fb944b6c39234611c5e871c0cee427e80a