conspiracion/rtl/cache, branch masterLinux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator.rtl/cache: fix critical bus protocol bug when caches are disabled2024-02-20T17:11:18+00:00Alejandro Sotoalejandro@34project.org2024-02-13T13:22:01+00:009bf55b70a85e5c12e9cfd0b8c7e1eaf1c05a6c1c
cache_core_waitrequest must be always high when caches are disabled.
Otherwise, cache_routing won't raise core_waitrequest on the idle state.
cache_core_waitrequest must be always high when caches are disabled.
Otherwise, cache_routing won't raise core_waitrequest on the idle state.
rtl/cache: disable ring when cache is itself disabled2024-02-20T17:11:18+00:00Alejandro Sotoalejandro@34project.org2024-02-13T13:21:43+00:007a639d4557a31337972e47d7d1f667b02b116770
rtl: refactor filenames and directory hierarchy2024-02-20T17:11:17+00:00Alejandro Sotoalejandro@34project.org2024-01-21T12:23:46+00:00f3b18ead59ae02f95dabbf0a1dea40873a816975
platform: implement support for disabling CPUs2023-10-28T08:29:46+00:00Alejandro Sotoalejandro@34project.org2023-10-28T08:29:46+00:0098d493f9c80f356cdbc2669150d772e451c3b80e
rtl/cache: split mem.sv out of cache_control.sv2023-10-06T21:43:37+00:00Alejandro Sotoalejandro@34project.org2023-10-06T21:41:52+00:0095770fcd6224b54666ec14480bcbebb6e39a7b5f
rtl/cache: split ring.sv out of cache_control.sv2023-10-06T14:56:38+00:00Alejandro Sotoalejandro@34project.org2023-10-06T14:56:38+00:0071df72cbe6fdfd65e5f7e3eb82bbeb76815b1ee7
rtl/cache: split token.sv out of cache_control.vs2023-10-06T14:24:51+00:00Alejandro Sotoalejandro@34project.org2023-10-06T14:24:19+00:008d22db83560d782c2f9e43e7359d7f616a3f4bb0