conspiracion/rtl/cache, branch ce4302/p2

conspiracion/rtl/cache, branch ce4302/p2 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. platform: implement support for disabling CPUs 2023-10-28T08:29:46+00:00 Alejandro Soto alejandro@34project.org 2023-10-28T08:29:46+00:00 98d493f9c80f356cdbc2669150d772e451c3b80e

rtl/cache: split mem.sv out of cache_control.sv 2023-10-06T21:43:37+00:00 Alejandro Soto alejandro@34project.org 2023-10-06T21:41:52+00:00 95770fcd6224b54666ec14480bcbebb6e39a7b5f

rtl/cache: split ring.sv out of cache_control.sv 2023-10-06T14:56:38+00:00 Alejandro Soto alejandro@34project.org 2023-10-06T14:56:38+00:00 71df72cbe6fdfd65e5f7e3eb82bbeb76815b1ee7

rtl/cache: split token.sv out of cache_control.vs 2023-10-06T14:24:51+00:00 Alejandro Soto alejandro@34project.org 2023-10-06T14:24:19+00:00 8d22db83560d782c2f9e43e7359d7f616a3f4bb0

rtl/perf: implement performance unit 2023-10-05T23:16:55+00:00 Alejandro Soto alejandro@34project.org 2023-10-05T22:26:26+00:00 d406720cecd7328f595255e65b6fd6b6814cefe4

cache control comments 2023-10-05T07:11:09+00:00 JulianCamacho jjulian.341@gmail.com 2023-10-05T07:11:09+00:00 955599919d88872512f1cc564619de586db43ea1

añade comentarios 2023-10-05T06:58:22+00:00 Fabian Montero fabian@posixlycorrect.com 2023-10-05T06:58:22+00:00 6f4837bace160fdeb0d1d378f179734fba4a92bc

actualiza comeenttarios de cache controler 2023-10-05T06:45:54+00:00 Fabian Montero fabian@posixlycorrect.com 2023-10-05T06:45:54+00:00 602b315b2891225b6c06e93621841d344039842f

añade comentarios 2023-10-05T06:22:05+00:00 Fabian Montero fabian@posixlycorrect.com 2023-10-05T06:22:05+00:00 347541479874ba00b2e671c577e8eadc5fc18d59

documeenta el anillo 2023-10-05T05:47:04+00:00 Fabian Montero fabian@posixlycorrect.com 2023-10-05T05:47:04+00:00 568079218823a92884146d3aee02e4e161d413e4