conspiracion/rtl/cache/routing.sv, branch ce4302/p2

conspiracion/rtl/cache/routing.sv, branch ce4302/p2 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. platform: implement support for disabling CPUs 2023-10-28T08:29:46+00:00 Alejandro Soto alejandro@34project.org 2023-10-28T08:29:46+00:00 98d493f9c80f356cdbc2669150d772e451c3b80e

rtl/perf: implement performance unit 2023-10-05T23:16:55+00:00 Alejandro Soto alejandro@34project.org 2023-10-05T22:26:26+00:00 d406720cecd7328f595255e65b6fd6b6814cefe4

explica mejor las transiciones de routing 2023-10-04T23:57:21+00:00 Fabian Montero fabian@posixlycorrect.com 2023-10-04T23:57:21+00:00 84ac4c10f1e3ca4f779a19a1b0a2c43c5e18e37d

explica estados de routing 2023-10-04T23:51:02+00:00 Fabian Montero fabian@posixlycorrect.com 2023-10-04T23:51:02+00:00 29832876ad224b7668ee1c2ba750e898fee347c3

routing and beginning cache control comments 2023-10-04T07:13:12+00:00 JulianCamacho jjulian.341@gmail.com 2023-10-04T07:13:12+00:00 dbe88c450b72913efc7831131cd92d27c9cc0b92

sram, offset and routing comments 2023-10-03T22:55:27+00:00 JulianCamacho jjulian.341@gmail.com 2023-10-03T22:55:27+00:00 bc466f0511d8b3029c0822f415ebc9ae152b9d09

comentarios 2023-10-03T07:39:00+00:00 JulianCamacho jjulian.341@gmail.com 2023-10-03T07:39:00+00:00 8c5a91578ca929f3a94b54628f6431c136dc417d

rtl/cache: fix writeback corruption 2023-09-25T22:56:06+00:00 Alejandro Soto alejandro@34project.org 2023-09-25T22:47:45+00:00 cd02f821525b8710dd37e2bc39a8a7dbc36ac4b0

rtl/cache: implement wait-for-reply 2023-09-25T11:08:58+00:00 Alejandro Soto alejandro@34project.org 2023-09-25T11:08:58+00:00 27978501a87c5bb7a9fd78e376e8f6772cad009e

rtl/cache: implement 2023-09-25T04:14:57+00:00 Alejandro Soto alejandro@34project.org 2023-09-25T02:58:04+00:00 15230c6cd2190a1efd61c2758bf56de37f3fe8da