conspiracion/rtl/cache/ring.sv, branch master

conspiracion/rtl/cache/ring.sv, branch master Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. rtl: refactor filenames and directory hierarchy 2024-02-20T17:11:17+00:00 Alejandro Soto alejandro@34project.org 2024-01-21T12:23:46+00:00 f3b18ead59ae02f95dabbf0a1dea40873a816975

rtl/cache: split mem.sv out of cache_control.sv 2023-10-06T21:43:37+00:00 Alejandro Soto alejandro@34project.org 2023-10-06T21:41:52+00:00 95770fcd6224b54666ec14480bcbebb6e39a7b5f

rtl/cache: split ring.sv out of cache_control.sv 2023-10-06T14:56:38+00:00 Alejandro Soto alejandro@34project.org 2023-10-06T14:56:38+00:00 71df72cbe6fdfd65e5f7e3eb82bbeb76815b1ee7