conspiracion/rtl/cache/defs.sv, branch master Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. rtl/perf: implement performance unit 2023-10-05T23:16:55+00:00 Alejandro Soto alejandro@34project.org 2023-10-05T22:26:26+00:00 d406720cecd7328f595255e65b6fd6b6814cefe4 






añade descripción de registro
2023-10-05T04:22:21+00:00

Fabian Montero
fabian@posixlycorrect.com

2023-10-05T04:22:21+00:00

fddab187c2370f66b02bd3f99cc258c8d5f7ce51












rtl/cache: increase to 64KiB per core
2023-10-04T22:29:41+00:00

Alejandro Soto
alejandro@34project.org

2023-10-04T22:29:41+00:00

5e1773191f8f2dc055c8b2b04afb74d2d3a4d7cf












rtl/cache: implement debug interface
2023-10-04T10:40:48+00:00

Alejandro Soto
alejandro@34project.org

2023-10-04T09:09:13+00:00

3de2c7e7dd214f80b8b9cca575e42e0b1b08034d












rtl: implement exclusive monitor datapath
2023-10-02T07:46:44+00:00

Alejandro Soto
alejandro@34project.org

2023-10-02T07:46:44+00:00

70d7dc9489f4d5b91d8138e0a341eec4ad7f15b0












platform: add CPUs and caches to qsys
2023-09-30T02:51:28+00:00

Alejandro Soto
alejandro@34project.org

2023-09-30T01:50:01+00:00

bc98bc905c2e796f0d587719196f7e4bf344510a












rtl/cache: implement wait-for-reply
2023-09-25T11:08:58+00:00

Alejandro Soto
alejandro@34project.org

2023-09-25T11:08:58+00:00

27978501a87c5bb7a9fd78e376e8f6772cad009e












rtl/cache: implement
2023-09-25T04:14:57+00:00

Alejandro Soto
alejandro@34project.org

2023-09-25T02:58:04+00:00

15230c6cd2190a1efd61c2758bf56de37f3fe8da