conspiracion/rtl/cache/control.sv, branch master Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. platform: add CPUs and caches to qsys 2023-09-30T02:51:28+00:00 Alejandro Soto alejandro@34project.org 2023-09-30T01:50:01+00:00 bc98bc905c2e796f0d587719196f7e4bf344510a 






rtl/cache: fix writeback corruption
2023-09-25T22:56:06+00:00

Alejandro Soto
alejandro@34project.org

2023-09-25T22:47:45+00:00

cd02f821525b8710dd37e2bc39a8a7dbc36ac4b0












rtl/cache: implement wait-for-reply
2023-09-25T11:08:58+00:00

Alejandro Soto
alejandro@34project.org

2023-09-25T11:08:58+00:00

27978501a87c5bb7a9fd78e376e8f6772cad009e












rtl/cache: implement
2023-09-25T04:14:57+00:00

Alejandro Soto
alejandro@34project.org

2023-09-25T02:58:04+00:00

15230c6cd2190a1efd61c2758bf56de37f3fe8da