conspiracion/rtl/cache/cache.sv, branch ce4302/p2

conspiracion/rtl/cache/cache.sv, branch ce4302/p2 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. platform: implement support for disabling CPUs 2023-10-28T08:29:46+00:00 Alejandro Soto alejandro@34project.org 2023-10-28T08:29:46+00:00 98d493f9c80f356cdbc2669150d772e451c3b80e

rtl/cache: split mem.sv out of cache_control.sv 2023-10-06T21:43:37+00:00 Alejandro Soto alejandro@34project.org 2023-10-06T21:41:52+00:00 95770fcd6224b54666ec14480bcbebb6e39a7b5f

rtl/cache: split ring.sv out of cache_control.sv 2023-10-06T14:56:38+00:00 Alejandro Soto alejandro@34project.org 2023-10-06T14:56:38+00:00 71df72cbe6fdfd65e5f7e3eb82bbeb76815b1ee7

rtl/cache: split token.sv out of cache_control.vs 2023-10-06T14:24:51+00:00 Alejandro Soto alejandro@34project.org 2023-10-06T14:24:19+00:00 8d22db83560d782c2f9e43e7359d7f616a3f4bb0

rtl/cache: implement debug interface 2023-10-04T10:40:48+00:00 Alejandro Soto alejandro@34project.org 2023-10-04T09:09:13+00:00 3de2c7e7dd214f80b8b9cca575e42e0b1b08034d

rtl/cache: implement ll/sc line monitor 2023-10-03T13:45:26+00:00 Alejandro Soto alejandro@34project.org 2023-10-03T13:45:12+00:00 f422a5fd9e83c69d4158a165edc47f45bcf600c4

rtl: implement exclusive monitor datapath 2023-10-02T07:46:44+00:00 Alejandro Soto alejandro@34project.org 2023-10-02T07:46:44+00:00 70d7dc9489f4d5b91d8138e0a341eec4ad7f15b0

platform: add CPUs and caches to qsys 2023-09-30T02:51:28+00:00 Alejandro Soto alejandro@34project.org 2023-09-30T01:50:01+00:00 bc98bc905c2e796f0d587719196f7e4bf344510a

rtl/cache: implement wait-for-reply 2023-09-25T11:08:58+00:00 Alejandro Soto alejandro@34project.org 2023-09-25T11:08:58+00:00 27978501a87c5bb7a9fd78e376e8f6772cad009e

rtl/cache: implement 2023-09-25T04:14:57+00:00 Alejandro Soto alejandro@34project.org 2023-09-25T02:58:04+00:00 15230c6cd2190a1efd61c2758bf56de37f3fe8da