conspiracion/rtl/bus_master.sv, branch ce4302/p2

conspiracion/rtl/bus_master.sv, branch ce4302/p2 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. rtl/core, tb: replace bus_master with a new top-level module 2023-09-26T03:33:49+00:00 Alejandro Soto alejandro@34project.org 2023-09-26T01:12:49+00:00 ed0bd705f94f6aea568ec8405534984a37770f21

Implemente byte-enable signal in stores 2022-11-16T05:31:30+00:00 Alejandro Soto alejandro@34project.org 2022-11-16T05:18:09+00:00 d9dfa098323bc9ffdc9e976bd4106efc75b2954a

Convert core state machines to Quartus-inferring RTL 2022-11-13T11:54:44+00:00 Alejandro Soto alejandro@34project.org 2022-11-13T11:22:23+00:00 d463acba5f9589085afb3dcc4058d82908ff90f2

Route cpu_rst_n signal through bus master 2022-11-13T11:54:44+00:00 Alejandro Soto alejandro@34project.org 2022-11-13T03:25:37+00:00 9a1dd87d89d3cb57fe0d811e462b9348234eae79

Fix reset glitches 2022-11-10T16:11:33+00:00 Alejandro Soto alejandro@34project.org 2022-11-10T16:11:33+00:00 acca3eb31a051f335c51306786bb972c21634998

Implement reset 2022-11-09T15:25:48+00:00 Alejandro Soto alejandro@34project.org 2022-11-09T15:25:48+00:00 5d798386c3b1c1dc45a2fbc382c9367ccc27c524

Add reset signal to bus master 2022-11-09T14:55:57+00:00 Alejandro Soto alejandro@34project.org 2022-11-09T14:25:40+00:00 5d8c9e67b1b37679823192201900507c3ba15d5b

Fix bus protocol errors in bus master 2022-11-09T13:47:51+00:00 Alejandro Soto alejandro@34project.org 2022-11-09T13:47:35+00:00 e2888796fae6f620e7774d598fe88b8ee48a5884

Fix handling of multi-cycle Avalon waitrequest states in bus master 2022-11-09T03:33:59+00:00 Alejandro Soto alejandro@34project.org 2022-11-09T03:33:59+00:00 1ea0519a2b6b81e0ba324cd69f8785735e7cbef5

Add bus master forward signals: irq, cpu_clk 2022-11-03T05:48:21+00:00 Alejandro Soto alejandro@34project.org 2022-11-03T05:48:21+00:00 abe3a7da04a3703bd504b5ed2e13ecc79dff4bd0