conspiracion/rtl/bus, branch ce3201

conspiracion/rtl/bus, branch ce3201 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Move bus/master.sv to bus_master.sv 2022-11-03T05:19:48+00:00 Alejandro Soto alejandro@34project.org 2022-11-03T05:19:48+00:00 4ef4190e67534168e1e64b810a09c0cd1338e2a9

Rework bus architecture 2022-10-16T01:31:55+00:00 Alejandro Soto alejandro@34project.org 2022-10-16T01:31:55+00:00 ec152d814af82524cf68df95d7f06b9b70c0d0d0

Rename data_rw to data_wr in bus master 2022-09-19T01:07:24+00:00 Alejandro Soto alejandro@34project.org 2022-09-19T01:07:24+00:00 b762fc978a49910986e00e6c08e0afbe1e612858

Fix memory simulation 2022-09-18T23:16:46+00:00 Alejandro Soto alejandro@34project.org 2022-09-18T23:16:46+00:00 503957e2883e754fc8424c420c3d9838bd639ed3

Update project structure to match Verilator Makefile 2022-09-18T04:10:39+00:00 Alejandro Soto alejandro@34project.org 2022-09-18T04:10:39+00:00 b0cb20496d88cd017c4c51243d16ac3b060cc1d6

Add Avalon bus master 2022-09-04T22:14:37+00:00 Alejandro Soto alejandro@34project.org 2022-09-04T22:14:37+00:00 fa3610a57e89dd667075cd8922a07a69ec433fa0