conspiracion/platform.qsys, branch ce3201 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Use 90MHz CPU clock 2022-12-20T04:35:16+00:00 Alejandro Soto alejandro@34project.org 2022-12-20T04:35:16+00:00 c410965f35c5fdccc135fb4802bb4d90c11d16ac 






Add interrupt controller to Platform Designer
2022-12-16T22:29:10+00:00

Alejandro Soto
alejandro@34project.org

2022-12-15T18:30:30+00:00

6e52e1df7567cdf419a193bf541dd98c0253e5a4












Bug fixes
2022-11-17T14:16:14+00:00

JulianCamacho
jjulian.341@gmail.com

2022-11-17T14:16:14+00:00

61bf2100fbd5e0a5f4bd1f013d70d8027604bbba












Replace vga_controller with streaming Altera IP
2022-11-15T22:25:49+00:00

Alejandro Soto
alejandro@34project.org

2022-11-15T22:25:41+00:00

044558e53d50ebd053abc76930723c9d7f606569












Fix VRAM clock
2022-11-15T05:32:46+00:00

Alejandro Soto
alejandro@34project.org

2022-11-15T05:32:46+00:00

22ef9a701d58d5e9d965793785241ad4aab29469












Add JTAG debug bridge
2022-11-15T04:05:40+00:00

Alejandro Soto
alejandro@34project.org

2022-11-15T04:05:40+00:00

c88433bb5572ee41864df76098ff913706a26387












Implement VGA controller
2022-11-15T03:09:19+00:00

Alejandro Soto
alejandro@34project.org

2022-11-14T04:37:10+00:00

cad870295dfb741d5c24c25016c5bba878bc37e5












Restore clock connections in Platform Designer
2022-11-13T12:53:53+00:00

Alejandro Soto
alejandro@34project.org

2022-11-13T12:53:53+00:00

bf746b3ee73081dff0da03a54749d1fd3c0215f6












Hardwire PLL reset to ground
2022-11-13T11:54:44+00:00

Alejandro Soto
alejandro@34project.org

2022-11-11T02:03:33+00:00

fb572d6cfb54ce212d2f43de00cb2702f0f433ce












Add debug instrumentation
2022-11-13T11:54:44+00:00

Alejandro Soto
alejandro@34project.org

2022-11-11T01:31:27+00:00

afb4f14f167b2b0cb6c270f04eaed310f78cccf3