conspiracion/core_hw.tcl, branch master Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. rtl/core/cp15: implement thread-local CP15 registers (from v7 spec), required for Linux SMP 2024-02-20T17:12:22+00:00 Alejandro Soto alejandro@34project.org 2024-02-13T18:15:24+00:00 641f52789a392f6370195003a04d6e674878628d 






rtl: refactor filenames and directory hierarchy
2024-02-20T17:11:17+00:00

Alejandro Soto
alejandro@34project.org

2024-01-21T12:23:46+00:00

f3b18ead59ae02f95dabbf0a1dea40873a816975












rtl/smp: implement SMP dead/alive handling
2023-11-16T22:43:59+00:00

Alejandro Soto
alejandro@34project.org

2023-11-16T01:10:34+00:00

87a42e555bf952047e287f4c7810cd538595d5af












platform: implement support for disabling CPUs
2023-10-28T08:29:46+00:00

Alejandro Soto
alejandro@34project.org

2023-10-28T08:29:46+00:00

98d493f9c80f356cdbc2669150d772e451c3b80e












rtl/core: implement ldrex/strex decode
2023-10-03T05:29:46+00:00

Alejandro Soto
alejandro@34project.org

2023-10-02T17:15:34+00:00

fbe3ab39675d338eb6d5388b7deacf98a3a8ae2d












rtl: implement exclusive monitor datapath
2023-10-02T07:46:44+00:00

Alejandro Soto
alejandro@34project.org

2023-10-02T07:46:44+00:00

70d7dc9489f4d5b91d8138e0a341eec4ad7f15b0












platform: implement SMP controller
2023-09-30T07:20:48+00:00

Alejandro Soto
alejandro@34project.org

2023-09-30T06:07:20+00:00

d1b10aa380578b5af20081dd37f2d36ec111cbd2












platform: add CPUs and caches to qsys
2023-09-30T02:51:28+00:00

Alejandro Soto
alejandro@34project.org

2023-09-30T01:50:01+00:00

bc98bc905c2e796f0d587719196f7e4bf344510a












rtl/core, tb: replace bus_master with a new top-level module
2023-09-26T03:33:49+00:00

Alejandro Soto
alejandro@34project.org

2023-09-26T01:12:49+00:00

ed0bd705f94f6aea568ec8405534984a37770f21