conspiracion/conspiracion_bus_master_hw.tcl, branch ce3201 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Implemente byte-enable signal in stores 2022-11-16T05:31:30+00:00 Alejandro Soto alejandro@34project.org 2022-11-16T05:18:09+00:00 d9dfa098323bc9ffdc9e976bd4106efc75b2954a 






Route cpu_rst_n signal through bus master
2022-11-13T11:54:44+00:00

Alejandro Soto
alejandro@34project.org

2022-11-13T03:25:37+00:00

9a1dd87d89d3cb57fe0d811e462b9348234eae79












Add reset signal to bus master
2022-11-09T14:55:57+00:00

Alejandro Soto
alejandro@34project.org

2022-11-09T14:25:40+00:00

5d8c9e67b1b37679823192201900507c3ba15d5b












Add bus master forward signals: irq, cpu_clk
2022-11-03T05:48:21+00:00

Alejandro Soto
alejandro@34project.org

2022-11-03T05:48:21+00:00

abe3a7da04a3703bd504b5ed2e13ecc79dff4bd0












Move bus/master.sv to bus_master.sv
2022-11-03T05:19:48+00:00

Alejandro Soto
alejandro@34project.org

2022-11-03T05:19:48+00:00

4ef4190e67534168e1e64b810a09c0cd1338e2a9












Rework bus architecture
2022-10-16T01:31:55+00:00

Alejandro Soto
alejandro@34project.org

2022-10-16T01:31:55+00:00

ec152d814af82524cf68df95d7f06b9b70c0d0d0












Rename data_rw to data_wr in bus master
2022-09-19T01:07:24+00:00

Alejandro Soto
alejandro@34project.org

2022-09-19T01:07:24+00:00

b762fc978a49910986e00e6c08e0afbe1e612858












Add Avalon bus master
2022-09-04T22:14:37+00:00

Alejandro Soto
alejandro@34project.org

2022-09-04T22:14:37+00:00

fa3610a57e89dd667075cd8922a07a69ec433fa0