conspiracion/conspiracion.sdc, branch ce4302/p2 Linux-capable SoC platform with a custom ARMv4 quad-core SMP CPU, coherent caches, and a 3D graphics accelerator. Synthesizes for Terasic DE-series FPGA boards. Simulated with Verilator. Use PLL output as CPU clock 2022-11-03T05:51:35+00:00 Alejandro Soto alejandro@34project.org 2022-11-03T05:51:35+00:00 64d84527cd71c3f96018df8831dcba38623d2e93 






Set core clock target to 100MHz
2022-10-16T06:39:17+00:00

Alejandro Soto
alejandro@34project.org

2022-10-16T06:39:17+00:00

0782a4f841a15f60c99d817cf82ce4fd3c2e9e3d












Fix timing analysis file
2022-09-24T06:22:09+00:00

Alejandro Soto
alejandro@34project.org

2022-09-24T06:22:09+00:00

5e5707f0efa72577513a1f06d91c3f14e5c407d6












Add .sdc for timing analysis
2022-09-20T02:28:27+00:00

Alejandro Soto
alejandro@34project.org

2022-09-20T02:28:27+00:00

6fd6c7173908d6c949375092786bfcef3e24cf90